/**
 * 模块功能：plus 一个周期高电平输入，delay N个高电平输出，N为count_ms *50_000
*/
module delay (
    input           clk_50m,
    input           rst_n,
    input           plus,
    input [9:0]     count_ms,//毫秒数
    output reg      delay
);

    localparam T_1ms = 50_000;
    reg [31:0] cnt = 0;
    reg flag = 0;

    always @(posedge clk_50m or negedge rst_n) begin
        if (!rst_n) cnt <= 0;
        else if ((cnt == count_ms * T_1ms - 1) || flag == 0) begin
            cnt <= 0;
            delay <= 0;
        end else if (flag == 1) begin
            cnt <= cnt + 1;
            delay <= 1;
        end
    end

    always @(posedge clk_50m or negedge rst_n) begin
        if (!rst_n) flag <= 0;
        else if (cnt == count_ms * T_1ms - 1) flag <= 0;
        else if (plus) flag <= 1;
        else flag <= flag;
    end

endmodule  //delay